1. Field of the Invention
The invention relates to an integrated circuit, more particularly to a CMOS tristate input/output buffer which is compatible with a 5 volt input signal at its output node while operating with a 3 volt power supply.
2. Description of the Related Art
Conventional tristate input/output buffers typically have power supplies in the 3 to 3.3 volt range and can tolerate logic input signals not exceeding the power supply voltage at the tristate output node. The output buffer receives an enable and data input, and puts a powered-up copy of the input data on the tristate output node, to be driven off-chip. When the output buffer is disabled the output node is at a high impedance and an input signal (typically from off-chip) can be applied to it. An input buffer for receiving that input signal is attached to aforementioned output node and that input signal is amplified for distribution within the chip.
A circuit of such a tristate input/output buffer is shown in FIG. 1 and will be explained next. The input/output buffer consists of output buffer 110 and input buffer 120. Output buffer 110 has a signal input 101 (OE), a signal input 102 (IN), and a tristate output node I/O, which provides an inverted copy of signal input IN. Output node I/O in turn is connected to a pad 103. Signal input 101 (OE, Output Enable) connects to the inverting input of OR gate 111 and to AND gate 112. Node DP, the output of OR gate 111, connect s to the gate of p-channel transistor 113 (MP1). Transistor 113 has its source-drain connected between voltage supply 108 (V.sub.DD, typically +3 volt) and tristate output node I/O. Node DN, the output of AND gate 112, is connected to the gate of n-channel transistor 114 (MN1). The drain-source path of transistor 114 is connected between output node I/O and reference voltage 109 respectively. Reference potential 109 is typically ground. Output node I/O is typically connected to a chip pad 103 from where the data then goes off-chip.
Input buffer 210 receives logic signal input CHIPIN at its input, which is connected to output node I/O. Output 104 (OIN) provides an inverted copy of input CHIPIN. The input of input buffer 120 is connected to the gates of p-channel transistor 121 (MP2) and n-channel transistor 122 (MN2). Transistor 121 has its source-drain path connected between power supply 108 (V.sub.DD, typically +3 volt) and output OIN. N-channel transistor 122 has its drain-source path connected between output OIN and reference potential 109 (typically ground). Input buffer 210 provides the inverted copy of signal CHIPIN to other circuits on the chip, which are not shown.
Still referring to FIG. 1, we explain the operation of logic gates 111, 112 and transistors 113 and 114. When input 101 (OE) is at logical "0", node DP is high and node DN is near ground, thus turning off transistors 113 and 114. Conversely, when OE is at logical "1" (Enable) and if IN is at logical "0", DP and DN are at "0" and MP1 is on and MN1 is off, causing output node I/O to swing to near +3 volt (logical "1"). If IN, however, is at logical "1", DP and DN are at "1" and MP1 is off and MN1 is on, causing output node I/O to go to near ground (logical "0"). I.e. the output buffer is a CMOS inverter driven by the truth table for logic gates 111 and 112. Input buffer 120 is a simple CMOS inverter that accepts input from either the output buffer or from pad 103.
The described tristate input/output buffer works within the confinement that an input signal at output node I/O cannot exceed the voltage of power supply 108 (typically +3 volt) by much. Else the drain of the p-channel transistor of the CMOS inverter becomes more positive than its gate and starts to conduct in the direction of drain to source. Referring now to FIG. 2, we show the output stage of the tristate input/output buffer. Added across transistors 113 (MP1) and 114 (MN1) are the parasitic diodes 115 (DN1) and 116 (DP1), respectively. Parasitic diode DN1 is created by the p.sup.+ drain to N-well junction, while parasitic diode DP1 is created by the n.sup.+ drain to P-substrate junction. If output node I/O becomes more positive than the power supply 108 the parasitic diode 115 also conducts. This causes undesirable power consumption and heavy loading of the input at output node I/O.
Other related art teaches the use of N-well switching for tristate input/output buffers where the off-chip driver is designed in a lower supply voltage than is the circuit of the external signal which is applied to the buffer output node. One such example is U.S. Pat. No. 5,151,619 (Austin et al.) which uses a control transistor to raise the voltage of the N-well and also includes a transmission-gate; both are added to insure that the pull-up transistor is turned off when the voltage at the buffer output rises above the power supply voltage. U.S. Pat. No. 5,467,031 (Nguyen et al.) is designed to overcome various drawbacks of the related art and of the above cited patent, U.S. Pat. No. 5,151,619 (Austin et al.), by providing a tristate driver circuit that is substantially more stable and provides higher drive power at the cost of adding many more transistors and using a lot of chip real estate. U.S. Pat. No. 5,266,849 (Kitahara et al.) provides another tristate buffer circuit using a low voltage driver, a high level output driver, a feedback loop, an N-well voltage controller and other circuit elements to improve output frequency performance, to protect the buffer output device from excessive gate to drain voltages, and to prevent forward biasing of its parasitic diode. However, the number of transistors, just in the output buffer, exceeds 20.